Passivation for cleaning a material

ABSTRACT

A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define “best fit” lines on that graph. For a given dip time, a first line representing the prepassivation+etchant/etch retardant clean is 30 to 40 Angstroms lower than a second line representing the prior art clean using the etchant/etch retardant without prepassivation. Accordingly, the first line&#39;s Y-axis intercept, representing the “zero dip time,” is also 30 to 40 Angstroms lower than the second line&#39;s zero dip time.

TECHNICAL FIELD

[0001] The present invention relates generally to cleaning methods used in the fabrication of semiconductor devices. More particularly, the present invention pertains to protecting at least one material while removing at least one other material from a workpiece during the fabrication of a semiconductor device.

BACKGROUND OF THE INVENTION

[0002] The fabrication of semiconductor devices often involves providing materials over a substrate and shaping those materials through processes such as photolithography and etching. In the current application, the term “substrate” or “semiconductor substrate” will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). Further, the term “substrate” also refers to any supporting structure including, but not limited to, the semiconductive substrates described above. Moreover, it is understood that a semiconductor device may comprise conductive and insulative materials as well as a semiconductive material. While etching a semiconductor device, more than one type of material included as part of that device may be exposed to the etching environment, although it may not be desirable to etch all of the exposed materials at the same rate. In fact, some sort of etch selectivity is often preferable.

[0003] One example in which etch selectivity is desired involves processing a silicon wafer serving as the substrate, wherein processing is for purposes of constructing a memory device. A doped oxide can be deposited over the silicon substrate using methods known in the art. This doped oxide could be a tetraethylorthosilicate (TEOS) based glass, borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), an arsenic-doped silicon oxide, or some other doped oxide. For purposes of clearly explaining the current invention and its background, it is assumed that BPSG is deposited over the silicon substrate. At least one opening is then formed through the BPSG down to the substrate. This opening may be formed using an etch process as guided by a patterned mask layer over the BPSG. Again, such masking, patterning, and etching processes are known in the art. The resulting patterned BPSG layer allows for a conductive layer to be subsequently deposited, wherein the remaining BPSG portions electrically isolate the conductive material from the substrate, while the opening in the BPSG allows for electrical communication between the conductive material and the substrate. Because this opening allows for electrical contact between different layers, the opening itself is often referred to as a “contact” both in the art and in this specification.

[0004] However, before such a conductive layer is deposited, conditions may be present that would interfere with electrical communication between the silicon substrate and the conductive layer to be deposited. For example, once a contact has been etched through the BPSG down to the silicon substrate, the uncovered silicon may be exposed to an oxidizing environment. Such an occurrence may take place in the form of cleaning an organic contaminant from the in-process device. In the presence of sufficient energy, such as thermal energy or that derived from a plasma ambient or an oxidizing liquid ambient, the exposed silicon reacts to form a silicon oxide, such as SiO₂. Because the oxide is formed from a chemical reaction with an integral portion of the in-process device, the oxide may be referred to as a “native” or “chemical” oxide that has been “grown” or formed. This is in contrast to a deposited oxide, wherein a deposition process, such as chemical vapor deposition (CVD), provides an oxide layer that is discrete from the in-process device's previously existing structures. The BPSG layer mentioned above is an example of a deposited oxide. In providing an oxide in this manner, a dopant is often added to the ambient during the deposition process and ends up incorporated as part of the oxide. On the other hand, “native” or “chemical” oxides are undoped. Further, such oxides are electrical insulators. Accordingly, if any such oxide is allowed to remain at the bottom of the contact, it will hinder electrical communication between the substrate and a subsequently deposited conductive material.

[0005] As a result, in-process devices at this stage of fabrication often undergo cleaning steps to remove the native oxide at the bottom of the contact prior to depositing conductive material. One exemplary cleaning process known in the art concerns the use of solutions including hydrofluoric acid (HF). Either through immersion, spraying, vapor treatment, or other methods, the native oxide of the in-process device is exposed to and etched by the HF solution. The HF cleaning may be performed before, after, or between other cleaning steps performed with other solutions, such as an RCA clean, to provide a hydrogen passivated, hydrophobic, oxide-free surface.

[0006] Unfortunately, while HF etches the native oxide from the bottom of the contact, it also etches other oxides, including the deposited BPSG that defines the contact. In fact, a standard HF cleaning solution containing 300 parts H₂O to 1 part HF etches BPSG over native oxide at an etch ratio of 10:1. The result is that the contact's diameter is increased. Widening the contact is detrimental to semiconductor device fabrication, as the contact may be near conductive structures such as the conductive electrode of a capacitor. Because the opening will also be filled with a conductive material, a wider contact means that the two conductive elements will be closer, and the likelihood of a short between the two will therefore be increased, especially in the event of a misalignment in the fabrication process. This is even more of a problem if other processes also widen the contact. In fabricating a dynamic random access memory (DRAM), current process flows call for a contact that is 0.25 microns in diameter and is laterally spaced from a capacitor plate by only about 0.06 to 0.08 microns. Accordingly, any improvements that allow for less of an increase in the contact's diameter are appreciated. In addition, there is a constant need in the industry to fabricate ever-smaller devices in order to maximize the efficient use of the wafer's surface area. This need can be achieved by shrinking the dimension of features, such as the contact diameter. It follows that, once a feature's dimension has been established, it is desired to avoid processes that may increase that dimension. Further, etching the BPSG will also reduce the vertical thickness of the BPSG layer. At current device sizes, reduction in thickness is not as critical a problem as the increase in contact diameter. Nevertheless, thinning the BPSG may be undesirable in certain circumstances. Thus, for these reasons as well as others, those skilled in the art look for ways to eliminate or at least reduce the widening of the contact in the BPSG that occurs while cleaning the bottom of the contact.

[0007] The use of other cleaning agents with a more favorable etch selectivity is one way to do so. One cleaning solution known in the industry comprises 30% ammonium fluoride by weight, 1% phosphoric acid, and 69% H₂O. This solution has an etch selectivity ratio of 1.5:1, still in favor of BPSG. One vendor identifies this solution as “QE II.” Another cleaning solution, comprising 30% ammonium fluoride by weight, 3% phosphoric acid, and 67% H₂O, has an etch selectivity ratio of 1:1. This solution is sometimes identified as “Super Q.”

[0008] Another way to improve etch selectivity is to include an etch retardant in the etching/cleaning solution. Without limiting this or any other invention, it is believed that doing so creates competing reactions, with the etch retardant passivating the BPSG and the etchant etching the BPSG and other oxides, that results in a better etch selectivity in favor of undoped native oxide as opposed to doped deposited oxide. One such solution combines HF; H₂O; and a component identified as (R)₄NOH, wherein R=(C₁-C₂₀)alkyl and is preferably tetra ethyl ammonium hydroxide (TEAH) or tetra methyl ammonium hydroxide (TMAH). This chemical is addressed in greater detail in U.S. Pat. No. 5,783,495 by Li et al. and assigned to Micron Technology, Inc. BPSG/native oxide selectivity ratios based on Li's teachings are known to range from 0.5:1 to 2:1. Another selective oxide etchant (identified by one vendor as SOE) achieves a BPSG/native oxide etch selectivity ratio of 0.8:1 using a combination of about 94% glycol by weight, about 5% ammonium fluoride, and about 1% iminodiacetic acid. Iminodiacetic acid is an iminopolycarboxylic acid and, more generally, an iminocarboxylic acid. Iminodiacetic acid may be identified by a molecular formula C₄H₇NO₄, while a linear formula for iminodiacetic acid is HN(CH₂CO₂H)₂. An exemplary structure for iminodiacetic acid follows.

[0009] While these methods are useful in fabrication of semiconductor devices as well as other workpieces, there is nevertheless a constant need in the art to further reduce the amount of etching experienced by one type of oxide during a time in which another type of oxide is being etched. More generally, it is desired in the art to reduce the effect of a process on one material while that process acts upon another material.

SUMMARY OF THE INVENTION

[0010] Accordingly, the present invention provides for modifying a material in relation to a processing step. In some exemplary embodiments, the surface of a workpiece's doped deposited oxide is passivated before exposing it to an etchant. In more specific embodiments of this type, a silicon wafer having a patterned doped oxide deposited thereon is dipped into an etch retardant prior to dipping the wafer in a solution containing both the etch retardant and an oxide etchant.

[0011] Other exemplary embodiments concern a passivation process preceding a cleaning step, wherein the effects of the combined passivation/cleaning steps defme a “best fit” line on a chart displaying the change in the dimension of a workpiece's feature as a function of etch time. This line has a lower Y-axis intercept than does a line depicting the effect of the cleaning process without the exemplary passivation process, thereby indicating a preferable reduction in the amount of initial etching of the workpiece.

[0012] Still other embodiments encompass other prepassivation methods, postpassivation methods, and solutions and systems used therefor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 depicts a cross-sectional view of an in-process semiconductor device known in the art.

[0014]FIG. 2 illustrates a cross-sectional view of an in-process semiconductor device having undergone an exemplary process within the scope of the current invention.

[0015]FIG. 3 is a graph illustrating the change in contact diameter as a function of dip time for cleaning solutions known in the art.

[0016]FIG. 4 is another graph illustrating the change in contact diameter as a function of dip time resulting from an exemplary embodiment of the current invention in comparison with a prior art cleaning solution.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017]FIG. 1 depicts an in-process portion of a prior art semiconductor device comprising a silicon substrate 20 supporting a BPSG layer 22. A contact 24 has been etched through the BPSG 22, and a native oxide 26 has been formed from the portion of the silicon substrate 20 exposed by contact 24. Regardless of whether this native oxide 26 is intentionally formed or not, or whether the native oxide 26 is desirable at some point or not, it is assumed that by some step in the fabrication process, it is desired to remove the native oxide 26 with little if any effect on the BPSG. This result is pictured in FIG. 2. The effect of prior art attempts to achieve this result can be seen in the graph of FIG. 3. That figure displays the effect of various contact cleaning chemistries (CCS) in terms of the change in contact diameter as a function of the amount of time the silicon substrate remains dipped in a particular chemistry. The change in contact diameter (ΔCD) is measured along the Y-axis in Angstroms, and the dip time is measured along the X-axis in seconds. The diamond-shaped data points “♦” indicate measurements of the change in contact diameter after dipping the wafer in the aforementioned 30% ammonium fluoride/3% phosphoric acid cleaning solution for various lengths of time.

[0018] It is believed that, were it not for random errors in the experimental measurements, the data could be generally represented by a known mathematical function—specifically, an equation defining a straight line. However, due to these random errors, it is not possible to choose a straight line that agrees with all measurements. As a result, a line 25 has been chosen wherein the average of the squares of the vertical deviations of the diamond-shaped data points from the line 25 is as small as possible. This method of defining line 25 is a type of linear regression known as the “least squares” method, and the resulting line 25 is known as a “best fit” line. Accordingly, the data points were entered into a Microsoft Excel spreadsheet, which derived a graph representing the linear trend of these points using the least squares method. The graph in FIG. 3 is based upon that Excel graph. Similarly, the circular points, square-shaped points, and triangular points in FIG. 3 indicate treatments in dilute HF (300:1 in H₂O); 30% ammonium fluoride/1% phosphoric acid; and 94% glycol/5% ammonium fluoride/1% iminodiacetic acid respectively, and define best fit lines 27, 28, and 30 accordingly.

[0019] It should be understood, however, that while these lines 25, 27, 28, and 30 serve as general guidelines illustrating the effect of various cleaning agents, the lines 25, 27, 28, and 30 do not necessarily reflect the etching during the entire cleaning process. For instance, it can be seen that none of the of lines 25, 27, 28, and 30 intercept the Y-axis at the point representing 0 angstroms. Rather, lines 25, 27, 28, and 30 intercept that axis at points representing changes in contact diameter (CD) greater than zero angstroms. Thus, a literal interpretation of the graph would suggest that the CD will change (widen) even though the dip time is zero (i.e. with no cleaning). However, without limiting the current invention, the inventor understands that the non-zero intercept instead suggests that the CD changes at a greater rate at the initiation of cleaning, and that this rate eventually decreases to the relatively constant rate indicated by the slopes of lines 25, 27, 28, and 30. The high rate of ΔCD per unit time at the initiation of cleaning, in turn, suggests that the BPSG is initially undergoing some form of enhanced etching that does not occur later in the cleaning process.

[0020] Again, without limiting the current invention, it is believed that, in cleaning processes using a solution comprising both an etch retardant and an etchant, it may be that the etchant is reacting with the BPSG faster than the etch retardant is able to begin protecting the BPSG. Once the etch retardant has had time to take effect, the slope of line 30, for instance, becomes lower and changes less. Before that time, however, etching without the benefit of the etch retardant's protective properties may be responsible for the enhanced etching. Moreover, a similar phenomenon may occur at the end of the cleaning process, when the wafer is no longer immersed in the cleaning agent and is subsequently rinsed with deionized water. At that stage of the process, the etch retardant may be leaving the BPSG surface faster than the etchant, leaving the remains of the etchant to act upon the BPSG without the benefit of the etch retardant.

[0021] Regardless of the reason for the non-zero Y-intercept of lines 25, 27, 28, and 30 in FIG. 3, at least one exemplary embodiment of the current invention serves to lower the Y-intercept by passivating the BPSG before exposing it to an etchant. A preferred exemplary embodiment concerns treating the in-process semiconductor device comprising the patterned BPSG layer over a silicon substrate that is to be dipped in the glycol/ammonium fluoride/iminodiacetic acid solution. Specifically, before the wafer is exposed to that solution, it is first immersed in a solution that is similar but lacking the ammonium fluoride etchant. More specifically, the wafer is immersed in a glycol matrix containing the iminodiacetic acid surface modifying agent. In this embodiment, the iminodiacetic acid represents up to about 1% of the total weight of the solution. Immersion takes place at a temperature ranging from 15° C. to 35° C. (preferably 25° C.) for a time ranging from 1 to 10 minutes (preferably 5 minutes). Concerning the preferred temperature, it should be noted that 25° C. is also the optimum temperature for the subsequent treatment in glycol/ammonium fluoride/iminodiacetic acid. As for the time, it should be appreciated that the time required to prepassivate the BPSG will vary depending upon the concentrations of the components of the surface modifying solution.

[0022] Without limiting the invention, it is believed that the iminodiacetic acid bonds to the boron sites on the BPSG surface, thereby sterically hindering the ability of fluorine to attack the BPSG. More specifically, it is believed that a portion of a given iminodiacetic acid molecule associates with boron in the BPSG, with another portion of the iminodiacetic acid molecule extending over an oxide portion of the BPSG. Thus, when fluorine is introduced, its effect on the BPSG's oxide is hindered by the fact that the iminodiacetic acid is physically interposed between the fluorine and a portion of the BPSG's oxide.

[0023] It is further theorized that iminodiacetic acid forms a monolayer—a continuous layer having the thickness of at most single iminodiacetic acid molecule—over the BPSG. It is also possible that the iminodiacetic acid molecules forming the monolayer may have been altered from the HN(CH₂CO₂H)₂ formula disclosed above. For example, it is possible that a particular iminodiacetic acid loses a hydrogen atom at some point before or after associating with the BPSG.

[0024] Regardless of the exact interaction between BPSG and iminodiacetic acid, the theorized result of cleaning in glycol/ammonium fluoride/iminodiacetic acid after this prepassivation is depicted by line 30′ in the chart of FIG. 4. A comparison with line 30 demonstrates that the expected ACD for any given time is 30 to 40 Angstroms lower using the prepassivation process of this exemplary embodiment. Accordingly, the Y-intercept of line 30′ is 30 to 40 Angstroms lower, indicating a lessening of the enhanced etching suffered during the initiation of the cleaning process. It is preferred, although not required, that this prepassivation step occur immediately before the cleaning step, with no intervening process.

[0025] In another exemplary embodiment, the wafer is immersed in an etch reducing component having the formula (R)₄NOH, wherein R=(C₁-C₂₀)alkyl. This is done before exposing the wafer to a solution containing that etch reducing component along with an etchant. In a more specific exemplary embodiment, the wafer is dipped in TMAH before dipping it in a TMAH/HF cleaner. In another specific exemplary embodiment, the wafer is dipped in TEAH before dipping it in a TEAH/HF cleaner. While it is expected that these embodiments will lower the change in contact diameter for a given dip time, it is theorized that at least one reason for this result is that the TMAH or TEAH chemically reacts to neutralize the HF. Such a reaction risks preventing adequate cleaning. Thus, care should be taken to avoid over-protecting the wafer. This can be achieved by methods known in the art such as diluting the TMAH or TEAH bath or by using a vapor or a spray to minimize the volume of TMAH or TEAH available for reaction with the HF.

[0026] These exemplary embodiments demonstrate that, if the wafer is to be exposed to a combination etchant/etch retardant, it is preferred to first immerse the wafer in the same etch retardant that is to be used in that combination. This is not a requirement for the invention, however, as other etch retardants could be used for the prepassivation process so long as they do not react with the chemicals of the subsequent cleaning process or another process to the detriment of the completed semiconductor device.

[0027] It should also be noted that, in the exemplary embodiment discussed above concerning glycol/ammonium fluoride/iminodiacetic acid, the wafer is prepassivated in a solution comprising all chemicals making up the glycol/ammonium fluoride/iminodiacetic acid with the exception of the etchant; specifically, the wafer is treated in iminodiacetic acid and glycol. Other embodiments, however, allow for treatment in the etch retardant alone, the etch retardant with only some of the chemicals of the cleaner, or the etch retardant with other chemicals that do not appear in the cleaner. Again, it is desired that the chemicals of the prepassivation treatment do not react with those of the cleaning treatment or other process in a manner that will adversely affect the completed semiconductor device.

[0028] Moreover, it is not necessary that the wafer be immersed in a surface modifying agent, as exemplary embodiments of the current invention allow for the use of other methods to expose the wafer to a modifying agent. For example, it is possible to spray an etch retardant onto the wafer before cleaning it. Moreover, such spraying may involve centrifugal spraying or high pressure spraying methods as well as others. Additionally, the etch retardant could be applied in a vapor cleaning system.

[0029] Additionally, rather than moving the wafer to different chemical environments, exemplary embodiments of the current invention also address maintaining the wafer in a stationary position and altering the chemistry surrounding the wafer. For example, instead of dipping a wafer into a tank of glycol/iminodiacetic acid and then into a tank of glycol/ammonium fluoride/iminodiacetic acid, one could place a wafer in a single tank initially containing a solution of glycol/iminodiacetic acid. Ammonium fluoride could then be added to the solution over time until the desired etch characteristics are achieved. Further, the amount of ammonium fluoride could then be reduced until a solution comprising mostly glycol/iminodiacetic acid exists in the tank once more. Cleaning tanks configured to receive multiple fluids are known in the art, as disclosed by U.S. Pat. No. 4,899,767, assigned to CFM Technologies, Inc. Such tanks could be modified to achieve exemplary embodiments included within the scope of the invention. Other embodiments involving changing the ambient chemistry around the wafer involve the use of spraying devices, vapor cleaning systems, or other delivery devices known in the art.

[0030] The exemplary embodiments described above, as well as others, benefit the formation of a device wherein it is sought to remove a native material yet minimize the removal of a deposited material of that device. In addition, such embodiments may be applied wherein it is sought to remove an undoped material of a device yet minimize the removal of a doped material of that device. Exemplary embodiments have still other applications in circumstances concerning the removal of a material formed predominantly by the use of thermal energy while minimizing the removal of a material formed by some alternative process. This alternative process may use thermal energy but may also depend on parameters beyond mere heat and an oxygen source. For example, additional precursor and reactant gases may be required to provide the material.

[0031] Further, given the ability of the above described exemplary embodiments to passivate doped deposited oxide in preparation for etching an undoped native oxide, it should be noted that other embodiments of the current invention include passivating doped deposited oxide in preparation for etching a material other than an oxide and in preparation for a process other than etching.

[0032] In addition, the native oxide to be etched in the above exemplary embodiments is a side effect of the processes used to fabricate a semiconductor device. The current invention, however, also includes within its scope embodiments wherein a doped oxide portion of a device is protected while etching a native or thermal or grown oxide serving as a particular component of the device.

[0033] Still other exemplary embodiments concern allowing selective etching of one portion of a material incorporating a first dopant over a second portion of the material incorporating a second dopant. Moreover, the material need not be an oxide. For example, given a workpiece comprising n+ and p+ polycrystalline silicon regions, passivating the workpiece with iminodiacetic acid solution before exposing the workpiece to an etchant will help protect the p+ regions while the n+ regions are etched. In a preferred exemplary embodiment of this type, the p+ region achieves that state by way of a boron implant or by in situ boron doping during a poly deposition process, in which case the iminodiacetic acid is expected to interact with the boron as described above in other exemplary embodiments.

[0034] Furthermore, while many of the exemplary embodiments discussed above address a passivation step and etch/passivation step performed in series, it should be noted that the current invention does not require that the passivation step occur first in the series. Rather, exemplary embodiments also address a passivation step that occurs after the etch/passivation step. Preferably, such a passivation step occurs before rinsing the workpiece in deionized water. As a specific example, after dipping a wafer in a glycol/ammonium fluoride/iminodiacetic acid, the wafer could then be dipped in glycol/iminodiacetic acid. It follows that exemplary embodiments of the current invention also address circumstances wherein a workpiece is passivated both before and after etching. Also, if a passivating agent is included with the etchant, there could be passivation occurring before, during, and after etching. The current invention includes within its scope exemplary embodiments concerning passivation occurring at any of these times, either individually or in combination.

[0035] Moreover, one of ordinary skill in the art will appreciate that, although exemplary embodiments of this invention have been described above for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For example, embodiments of the current invention can serve to modify the surface of doped oxides other than BPSG, such as BSG, PSG, arsenic-doped oxides, and others. In addition, a dopant is not necessarily required in the material to be protected, as other exemplary embodiments concern physically or chemically associating the passivating agent with a component of the material. In some exemplary embodiments, this component could be an additive such as nitrogen.

[0036] Finally, it should be noted that exemplary embodiments have applications in semiconductor devices such as integrated circuit devices including memory devices, logic devices having embedded memory, application specific integrated circuits, microprocessors, microcontrollers, digital signal processors, and the like incorporating a memory array. It should be emphasized, however, that incorporation with a memory device is not necessary for at least some exemplary embodiments of the current invention. In addition, a memory or a memory module formed in accordance with the present invention may be employed in various types of information handling systems (network cards, telephones, scanners, facsimile machines, routers, televisions, video cassette recorders, copy machines, displays, printers, calculators, and personal computers, and the like incorporating memory). In more general terms, exemplary embodiments of the current invention has application to “tall” structures or devices with topography defining a high aspect ratio. For example, the contact 24 of the in-process device of FIG. 1 defines an opening that is 0.25 microns wide and 2.3 microns deep, thereby defining an aspect ratio of 9.2/1. Thus, while devices exhibiting any aspect ratio (or no aspect ratio at all) will benefit from exemplary embodiments of the invention, devices defining aspect ratios of around 5/1, 6/1 and especially 10/1 or greater receive particular benefit. Accordingly, the invention is not limited except as stated in the claims. 

What is claimed is:
 1. A pretreatment chemistry for a workpiece configured for treatment with a cleaning solution, comprising an etch retardant that is also present in said cleaning solution.
 2. The pretreatment chemistry in claim 1, wherein said etch retardant comprises an iminocarboxylic acid.
 3. The pretreatment chemistry in claim 2, wherein said etch retardant comprises an iminopolycarboxylic acid.
 4. The pretreatment chemistry in claim 3, wherein said etch retardant comprises HN(CH₂CO₂H)₂.
 5. The pretreatment chemistry in claim 3, wherein said etch retardant comprises C₄H₇NO₄.
 6. The pretreatment chemistry in claim 3, wherein said etch retardant comprises a material having a structural formula of


7. The pretreatment chemistry in claim 3, wherein said etch retardant comprises iminodiacetic acid.
 8. The pretreatment chemistry in claim 7, further comprising at least one other non-etchant component that also appears in said cleaning solution.
 9. The pretreatment chemistry in claim 8, further comprising all other non-etchant components that also appear in said cleaning solution.
 10. A method of cleaning a semiconductor workpiece, comprising: exposing a first portion of said semiconductor workpiece to a passivating agent; and etching a second portion of said semiconductor workpiece after said exposing step.
 11. The method in claim 10, wherein said etching step comprises etching said first portion of said semiconductor workpiece.
 12. The method in claim 10, wherein said etching step comprises introducing said second portion to said passivating agent.
 13. The method in claim 10, wherein said etching step comprises introducing said first portion to an additional amount of said passivating agent.
 14. The method in claim 10, wherein said exposing step further comprises exposing said second portion to said passivating agent.
 15. A method of passivating a semiconductor device including a structure, comprising: modifying a surface characteristic of said structure of said semiconductor device with an etch retardant, said etch retardant being included in a solution with an etchant; and premodifying said surface characteristic of said structure with said etch retardant, said etch retardant being included in a solution free of said etchant, said premodifying step occurring before said modifying step.
 16. The method in claim 15, wherein said premodifying step further comprises premodifying said surface characteristic of said structure with said etch retardant being included in a solution free of any etchant.
 17. A method of supplementing an etching process for a workpiece, wherein an analysis of said etching process alone indicates a first zero dip time etch progression value that is a positive number, said method comprising: providing a passivation process consecutive with said etching process, wherein an analysis of a combination of said passivation process and said etching process indicates a second zero dip time etch progression value that is less than said first zero dip time etch progression value; and subjecting said workpiece to said combination.
 18. A method of processing a semiconductor wafer including a feature having a dimension, comprising: dipping said semiconductor wafer in an etch retardant; and dipping said semiconductor wafer in an etchant after said step of dipping said semiconductor wafer in an etch retardant, where, in response to an examination of a combined effect of said dipping steps, said dipping steps are configured to cooperatively define a first equation in a graph illustrating a change in said dimension versus dip time; and where, in response to an examination of an effect of dipping said semiconductor wafer in said etchant without dipping said semiconductor wafer in said etch retardant, said effect of dipping said semiconductor wafer in said etchant is configured to define a second equation; and wherein said first equation results in a lower value than said second equation at at least one dip time.
 19. The method in claim 18, wherein said dipping steps are configured to cooperatively define a first line in said graph in response to said examination of said combined effect.
 20. The method in claim 19, wherein said dipping steps are configured to cooperatively define a best fit line in said graph in response to said examination of said combined effect.
 21. The method in claim 20, wherein said dipping steps are configured to cooperatively define a least squares line in said graph in response to said examination of said combined effect.
 22. The method in claim 21, wherein said dipping steps are configured to cooperatively define a first straight line in said graph in response to said examination of said combined effect.
 23. The method in claim 22, wherein said dipping steps are configured to cooperatively define a first straight line minimizing vertical offsets from actual data points resulting from said dipping steps.
 24. A method of preparing a semiconductor workpiece for a cleaning process, said semiconductor workpiece comprising a structure that defines a dimension; and where, in the event of an investigation of said cleaning process, said cleaning process is able to define a first mathematical equation representing changes in said dimension as a first function of cleaning time; and wherein said method comprises: exposing said structure to a surface modifying agent prior to initiating said cleaning process; and allowing a combination of said exposing step and said cleaning process, in the event of an investigation of said combination, to define a second mathematical equation representing changes in said dimension as a second function of cleaning time, wherein: said first mathematical equation result in a first value at a cleaning time, said second mathematical equation results in a second value at said cleaning time, and said second value is less than said first value.
 25. A method of altering an effect of dipping a semiconductor device in a cleaning solution, said device comprising a structure defining a contact, and said effect allowing for an analysis resulting in a first best fit line in a graph displaying change in contact diameter (Y-axis) as a function of dip time (X-axis), said first best fit line having a first slope and a first Y-axis intercept, and said method comprising: modifying a surface of said structure, said modifying step resulting in a modified effect of dipping said semiconductor device in said cleaning solution; and allowing said modified effect to define a second best fit line in said graph in response to an optional analysis of said modified effect, said second best fit line having a second Y-axis intercept lower than said first Y-axis intercept.
 26. The method in claim 25, wherein said allowing step comprises allowing said modified effect to define a second best fit line in said graph, said second best fit line having a second slope that is equal to said first slope.
 27. The method in claim 25, wherein said allowing step comprises allowing said modified effect to define a second best fit line in said graph, said second best fit line having a second Y-axis intercept representing a change in contact diameter that is at least 30 Angstroms less than that represented by said first Y-axis intercept.
 28. The method in claim 27, wherein said allowing step comprises allowing said modified effect to define a second best fit line in said graph, said second best fit line having a second Y-axis intercept representing a change in contact diameter that is 30 to 40 Angstroms less than that represented by said first Y-axis intercept.
 29. A method of treating a semiconductor device structure, comprising: providing a cleaner including an etchant; providing an etchant-free version of said cleaner; exposing said semiconductor device structure to said etchant-free version of said cleaner; and subsequently exposing said structure to said cleaner including said etchant.
 30. The method in claim 29, further comprising a step of rinsing said structure after said step of exposing said structure to said cleaner including said etchant.
 31. A method of affecting a selectivity characteristic of an etching process simultaneously acting upon a first material and a second material, comprising: simultaneously exposing said first material and said second material to a surface modifying agent; and selectively passivating said first material to the exclusion of said second material with said surface modifying agent, said passivating step occurring before said etching process.
 32. The method in claim 31, wherein said passivating step comprises selectively passivating a first deposited material rather than a second grown material.
 33. The method in claim 31, wherein said passivating step comprises selectively passivating a first doped material rather than a second undoped material.
 34. The method in claim 31, wherein said passivating step comprises selectively passivating a first material rather than a second thermal material, said first material being formed in a process alternative to a predominantly thermal process.
 35. The method in claim 31, wherein said passivating step comprises selectively passivating a first discrete material rather than a second native material.
 36. A method of treating an in-process semiconductor device, comprising: depositing a first oxide as a first part of said semiconductor device; growing a second oxide from a second part of said semiconductor device; protecting said first oxide from being etched; and etching said second oxide after said protecting step.
 37. The method in claim 36, wherein: said depositing step comprises depositing a first oxide over a substrate; said method further comprises exposing a portion of said substrate with an opening through said first oxide; and said growing step comprises growing said second oxide from said exposed portion of said substrate.
 38. The method of claim 37, wherein said step of protecting said first oxide comprises protecting at least some of said first oxide from being etched; and wherein said step of etching said second oxide comprises etching at least some of said first oxide.
 39. The method of claim 38, wherein said step of growing a second oxide comprises growing a silicon oxide.
 40. The method in claim 39, wherein said step of growing a second oxide comprises allowing said second oxide to grow.
 41. A method of processing a semiconductor device, comprising: forming a doped oxide as a first part of said semiconductor device; allowing an undoped oxide to form at a second part of said semiconductor device; providing a modification to a surface of said doped oxide; and exposing said doped oxide and said undoped oxide to an oxide etchant, wherein said exposing step is discrete from said modifying step, and wherein said doped oxide is protected from said etchant to a degree by said modification.
 42. A method of forming a semiconductor device, comprising: forming a first oxide for said semiconductor device by way of a predominantly thermal process; forming a second oxide for said semiconductor device by way of an alternate process in relation to said predominantly thermal process; exposing said first oxide and said second oxide to a passivation solution, wherein said solution has a greater effect on said second oxide than on said first oxide; and subsequently exposing said first oxide and said second oxide to an etching solution, wherein said etching solution has a lesser effect on said second oxide than on said first oxide, said lesser effect resulting from said step of exposing said first oxide and said second oxide to a passivation solution.
 43. The method in claim 42, wherein said step of exposing said first oxide and said second oxide to a passivation solution comprises establishing a modified surface for said second oxide; and wherein said step of subsequently exposing said first oxide and said second oxide to an etching solution comprises doing so wherein said etching solution has less of an effect on said modified surface than it would have on an unmodified surface of said second oxide.
 44. A method of pretreating a workpiece to be exposed to a cleaning agent, said cleaning agent comprising ammonium fluoride and iminodiacetic acid, and said method comprising: providing an etch retardant; and exposing said workpiece to said etch retardant prior to exposing said workpiece to said cleaning agent.
 45. The method in claim 44, further comprising a step of avoiding a chemical reaction with said etch retardant that results in an undesired characteristic of a device formed from said workpiece.
 46. The method in claim 44, wherein said step of providing an etch retardant comprises providing an etch retardant comprising iminodiacetic acid.
 47. The method in claim 46, wherein said step of providing an etch retardant comprises providing an etch retardant further comprising glycol.
 48. A method of treating a workpiece to be exposed to a cleaning agent, said cleaning agent comprising HF and a component having a formula (R)₄NOH, wherein R=(C₁-C₂₀)alkyl, said method comprising: providing an etch retardant comprising said component having said formula (R)₄NOH, wherein R=(C₁-C₂₀)alkyl; and exposing said workpiece to said etch retardant before exposing said workpiece to said cleaning agent.
 49. The method in claim 48, wherein said step of providing an etch retardant comprises providing an etch retardant comprising TMAH.
 50. The method in claim 48, wherein said step of providing an etch retardant comprises providing an etch retardant comprising TEAH.
 51. A method of preparing a contact for cleaning by an etchant/etch retardant combination, said method comprising: providing a solution comprising said etch retardant without said etchant; and exposing a structure defining said contact to said solution.
 52. The method in claim 51, wherein said exposing step comprises dipping said structure into said solution.
 53. The method in claim 51, wherein said exposing step comprises immersing said structure in said solution.
 54. The method in claim 51, wherein said exposing step comprises spraying said solution onto said structure.
 55. The method in claim 51, wherein said exposing step comprises applying said solution to said structure in a vapor cleaning system.
 56. A method of fabricating a semiconductor device, comprising: including a doped deposited oxide as part of said semiconductor device; subjecting said doped deposited oxide to a wet etch; and at least partially protecting said doped deposited oxide from an effect of said wet etch by modifying said doped deposited oxide before initiating said wet etch, wherein said modifying uses a chemical that is also used in said wet etch.
 57. The method in claim 56, wherein said subjecting step comprises subjecting said doped deposited oxide to a cleaning step.
 58. The method in claim 56, wherein said subjecting step comprises subjecting said doped deposited oxide to an oxide etching step.
 59. The method in claim 58, wherein said subjecting step comprises subjecting said doped deposited oxide to a native oxide etching step.
 60. A method of processing oxides of an in-process semiconductor device, comprising: forming a first oxide as part of said in-process semiconductor device; changing a surface characteristic of said first oxide; forming a second oxide as part of said in-process semiconductor device; removing at least a portion of said second oxide after said changing step; and removing at most a portion of said first oxide during said step of removing at least a portion of said second oxide.
 61. The method in claim 60, wherein said step of forming a second oxide comprises allowing a native oxide to grow.
 62. The method in claim 60, wherein said step of forming a second oxide comprises growing an oxide structure.
 63. A method of treating a semiconductor device, comprising: providing a doped oxide at a first part of said semiconductor device; providing an undoped oxide at a second part of said semiconductor device; exposing said doped oxide and said undoped oxide to a chemical that is configured to have a first effect on said doped oxide and a second effect on said undoped oxide; and lessening said first effect on said doped oxide by treating a surface of said doped oxide before exposing said doped oxide to said chemical.
 64. The method in claim 63, wherein said exposing step comprises exposing said doped oxide and said undoped oxide to a chemical that is configured to etch said doped oxide at a first etch rate and to etch said undoped oxide at a second etch rate.
 65. The method in claim 64, wherein said exposing step comprises exposing said doped oxide to a chemical comprising fluorine.
 66. The method in claim 65, wherein said lessening step comprises hindering an ability of said doped oxide to react with fluorine.
 67. The method in claim 66, wherein said hindering step comprises forming a monolayer of a passivating material onto said doped oxide.
 68. A method of processing an oxide, comprising: initiating a plurality of competing reactions with said oxide; and generating one of said plurality of competing reactions with said oxide to the exclusion of another of said plurality of competing reactions before said initiating step.
 69. The method in claim 68, wherein: said initiating step comprises: etching said oxide, and simultaneously passivating said oxide; and said generating step comprises prepassivating said oxide.
 70. The method in claim 69, wherein: said etching step comprises reacting an etch component with a dopant in said oxide; and said prepassivating step comprises bonding a passivation component to said dopant.
 71. The method in claim 70, wherein said bonding step comprises bonding said passivation component to a boron atom in said oxide.
 72. The method in claim 71, wherein said bonding step comprises bonding said passivation component to a boron atom in a BPSG material.
 73. The method in claim 72, wherein said bonding step comprises bonding said passivation component to a boron atom in a BSG material.
 74. A method of complementing a cleaning step for a semiconductor device, wherein said cleaning step is configured to be performed at at least one temperature, said method comprising: providing an etch retardant solution; and treating said semiconductor device with said etch retardant solution, said treating step occurring in sequence with said cleaning step.
 75. The method in claim 74, wherein said treating step comprises treating said semiconductor device at a temperature range encompassing said at least one temperature.
 76. The method in claim 75, wherein said treating step comprises treating said semiconductor device at a temperature range of about 15° C. to 35° C.
 77. The method in claim 76, wherein said treating step comprises treating said semiconductor device for a time ranging from about 1 to 10 minutes.
 78. A method of adding to a cleaning step for a semiconductor device, wherein said cleaning step uses a cleaning solution comprising an etchant combined with an etch retardant, and wherein said etch retardant represents a percentage of a total weight of said cleaning solution, said method comprising: providing an etch retardant solution comprising said etch retardant representing said percentage of a total weight of said etch retardant solution; and treating said semiconductor device with said etch retardant solution, said treating step occurring in sequence with said cleaning step.
 79. The method in claim 78, wherein said providing step comprises providing an etch retardant solution comprising an etch retardant representing up to about 1% of said total weight of said etch retardant solution.
 80. The method in claim 79, wherein said providing step comprises providing an etch retardant solution comprising up to 1% by weight of iminodiacetic acid.
 81. A method of processing a semiconductor workpiece, comprising: providing a semiconductor workpiece comprising a material, said material comprising a first region incorporating a first dopant and a second region free of said first dopant; exposing said material to a passivation agent; and interacting at least a portion of said passivation agent with said first dopant.
 82. The method in claim 81, wherein said interacting step comprises attaching said at least a portion of said passivation agent to said first region by way of said first dopant.
 83. The method in claim 82, wherein said providing step comprises providing a semiconductor workpiece comprising polycrystalline silicon.
 84. The method in claim 83, wherein said providing step comprises providing a semiconductor workpiece comprising polycrystalline silicon, said polycrystalline silicon comprising a first region incorporating boron.
 85. The method in claim 84, wherein said providing step comprises providing a semiconductor workpiece comprising polycrystalline silicon, said polycrystalline silicon comprising a second region incorporating a second dopant.
 86. The method in claim 85, wherein said providing step comprises providing a semiconductor workpiece comprising polycrystalline silicon, said polycrystalline silicon comprising a second region, wherein said second region is an n+ region.
 87. The method in claim 86, further comprising etching said material; and interfering with said etching using said at least a portion of said passivation agent.
 88. The method in claim 87, wherein said interfering step comprises allowing said at least a portion of said passivation agent to extend between said first region and an etch agent.
 89. A method of treating a semiconductor substrate, comprising: forming a first oxide from a chemical reaction with said semiconductor substrate; depositing a second oxide onto said substrate, said second oxide being formed from a chemical reaction excluding said substrate; and selectively passivating said second oxide in relation to said first oxide.
 90. The method in claim 89, further comprising a step of selectively etching said first oxide after said passivating step.
 91. A method of controlling an etch process for an in-process semiconductor device, comprising: associating a passivation agent with a first material of said in-process semiconductor device prior to said etch process; and avoiding associating said passivation agent with a second material of said in-process semiconductor device.
 92. The method in claim 91, wherein said step of associating a passivation agent comprises chemically associating said passivation agent with said first material.
 93. The method in claim 91, wherein said step of associating a passivation agent with a first material comprises associating said passivation agent with an additive included as a part of said first material.
 94. The method in claim 93, wherein said step of avoiding associating said passivation agent comprises providing a second material lacking said additive.
 95. The method in claim 94, wherein said step of associating said passivation agent with an additive comprises associating said passivation agent with a dopant.
 96. The method in claim 94, wherein said step of associating said passivation agent with an additive comprises associating said passivation agent with nitrogen.
 97. A method of affecting an aspect ratio of a structure forming a part of a semiconductor wafer, comprising: providing a first oxide over said semiconductor wafer; defining a structure with said first oxide, said structure having an aspect ratio; allowing a second oxide to form over said wafer; applying a cleaning agent to said second oxide; and protecting said structure of said first oxide from said cleaning agent prior to said applying step.
 98. The method in claim 97, wherein said step of defining a structure with said first oxide comprises defining a structure having an aspect ratio of at least 10/1.
 99. The method in claim 97, wherein said step of defining a structure with said first oxide comprises defining a structure having an aspect ratio of around 10/1.
 100. The method in claim 99, wherein said step of defining a structure with said first oxide comprises defining a structure having an aspect ratio of at least 9.2/1.
 101. A method of cleaning a semiconductor device comprising a first portion and an adjacent second portion, wherein said second portion comprises a first material that is unique with respect to said first portion and a second material that is common with respect to said first portion, said method comprising: exposing said first and second portion of said semiconductor device to a solution; using said solution, sterically hindering an ability of an etchant to react with said second material associated with said second portion; exposing said first and second portion to said etchant; and allowing said etchant to react with said second material associated with said first portion.
 102. The method in claim 101, wherein said step of exposing said first and second portion of said semiconductor device to a solution comprises exposing said first and second portion of said semiconductor device to a solution comprising a molecule; and said step of using said solution comprises: interacting a first portion of said molecule with said first material of said second portion, and extending a second portion of said molecule over said second material of said second portion.
 103. The method in claim 102, wherein said step of using said solution further comprises allowing for a separation of a third portion of said molecule from said second portion of said molecule.
 104. The method in claim 103, wherein said step of using said solution further comprises allowing for a separation of a hydrogen atom.
 105. A method of supplementing a cleaning process involving exposing a semiconductor workpiece to a first solution comprising an etchant, said method comprising: providing a second solution free of any material capable of discemable etching of said semiconductor workpiece, wherein said second solution is capable of passivating at most a portion of said workpiece; and exposing said workpiece to said second solution.
 106. The method in claim 105, wherein said exposing step further comprises exposing said workpiece to said second solution at at least one time selected from before exposing said workpiece to said etchant, during exposing said workpiece to said etchant, and after exposing said workpiece to said etchant.
 107. The method in claim 105, further comprising a step of rinsing said etchant from said workpiece; and wherein said exposing step further comprises exposing said workpiece to said second solution before said rinsing step.
 108. A method of introducing a plurality of chemical ambients to a semiconductor wafer, comprising: exposing at least one semiconductor wafer to a first chemical ambient containing a passivator and lacking an etchant; exposing said at least one semiconductor wafer to a second chemical ambient containing said passivator and an etchant subsequent to said step of exposing at least one semiconductor wafer to a first chemical ambient; and fixing said at least one semiconductor wafer in a stationary position throughout said exposing steps.
 109. The method of claim 108, wherein: said step of exposing at least one semiconductor wafer to a first chemical ambient comprises: placing said at least one semiconductor wafer in a tank, and filling said tank with a glycol/iminodiacetic acid solution; and said step of exposing said at least one semiconductor wafer to a second chemical ambient comprises adding ammonium fluoride in said tank.
 110. The method in claim 109, further comprising a step of restoring said first chemical ambient in said tank subsequent to said step of exposing said at least one semiconductor wafer to a second chemical ambient.
 111. A method of passivating a semiconductor device including a structure, comprising: premodifying a surface characteristic of said structure of said semiconductor device with an etch retardant in an etchant-free solution; and modifying said surface characteristic of said structure with a solution including said etch retardant and an etchant.
 112. A method of generally maintaining a dimension of a semiconductor structure, comprising: defining said dimension with a first material of said semiconductor structure; associating said first material with a passivator; exposing said semiconductor structure to an etchant; and preventing at least some of said etchant from associating with said first material.
 113. The method in claim 112, wherein said step of preventing at least some of said etchant from associating with said first material comprises chemically neutralizing at least some of said etchant using said passivator.
 114. The method in claim 112, wherein said step of preventing at least some of said etchant from associating with said first material comprises physically blocking at least some of said etchant from said first material using said passivator.
 115. The method in claim 114, further comprising: avoiding an association between said passivator and a second material of said semiconductor structure; and associating said etchant with said second material. 